Strain inducing multi-layer cap

Details Strain inducing multi-layer cap Strain inducing multi-layer cap

2008-04-29

2008-04-29

Ho, Tu-Tu (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Thin active physical layer which is

Heterojunction

C257S028000, C257S213000, C257SE29072

Reexamination Certificate

active

11187213

ABSTRACT:
A strained transistor includes a silicon transistor, an encapsulating layer of silicon insulating material with an outer surface, and a stress inducing multilayer cap deposited on the outer surface of the encapsulating layer with at least two layers including a layer of rare earth oxide and a layer including silicon. The stress inducing cap can be designed to provide either compressive strain or tensile strain and virtually any desired amount of strain without producing dislocations, defects, and fractures in the structure.

REFERENCES:
patent: 2005/0199958 (2005-09-01), Chen et al.
patent: 2005/0224879 (2005-10-01), Xiang
patent: 2005/0263825 (2005-12-01), Frohberg et al.
patent: 2006/0284282 (2006-12-01), Cunningham

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