Method and apparatus of inter-chip bus shared by message...

Multiplex communications – Pathfinding or routing – Switching a message which includes an address header

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C370S395700, C709S224000

Reexamination Certificate

active

09863318

ABSTRACT:
A system of switches having a memory/command bus having a first interface, a second interface and a third interface. A memory is connected to the third interface of the memory/command bus. The memory has a first memory address. A first switch monitors the memory/command bus and interprets information written to the first memory address as proxy information. The first switch is connected to the first interface of the memory/command bus. The second switch monitors the memory/command bus and interprets information written to the first memory address as proxy information. The second switch is connected to the second interface of the memory/command bus.

REFERENCES:
patent: 5278789 (1994-01-01), Inoue et al.
patent: 5390173 (1995-02-01), Spinney et al.
patent: 5414704 (1995-05-01), Spinney
patent: 5423015 (1995-06-01), Chung
patent: 5459717 (1995-10-01), Mullan et al.
patent: 5473607 (1995-12-01), Hausman et al.
patent: 5499295 (1996-03-01), Cooper
patent: 5524254 (1996-06-01), Morgan et al.
patent: 5555398 (1996-09-01), Raman
patent: 5568477 (1996-10-01), Galand et al.
patent: 5579301 (1996-11-01), Ganson et al.
patent: 5644784 (1997-07-01), Peek
patent: 5652579 (1997-07-01), Yamada et al.
patent: 5696899 (1997-12-01), Kalwitz
patent: 5742613 (1998-04-01), MacDonald
patent: 5748631 (1998-05-01), Bergantino et al.
patent: 5781549 (1998-07-01), Dai
patent: 5787084 (1998-07-01), Hoang et al.
patent: 5790539 (1998-08-01), Chao et al.
patent: 5802052 (1998-09-01), Venkataraman
patent: 5802287 (1998-09-01), Rostoker et al.
patent: 5825772 (1998-10-01), Dobbins et al.
patent: 5828653 (1998-10-01), Goss
patent: 5831980 (1998-11-01), Varma et al.
patent: 5842038 (1998-11-01), Williams et al.
patent: 5845081 (1998-12-01), Rangarajan et al.
patent: 5887187 (1999-03-01), Rostoker et al.
patent: 5892922 (1999-04-01), Lorenz
patent: 5898687 (1999-04-01), Harriman et al.
patent: 5909686 (1999-06-01), Muller et al.
patent: 5918074 (1999-06-01), Wright et al.
patent: 5920699 (1999-07-01), Bare
patent: 5940596 (1999-08-01), Rajan et al.
patent: 5987507 (1999-11-01), Creedon et al.
patent: 6011795 (2000-01-01), Varghese et al.
patent: 6041053 (2000-03-01), Douceur et al.
patent: 6041109 (2000-03-01), Cardy et al.
patent: 6061351 (2000-05-01), Erimli et al.
patent: 6111858 (2000-08-01), Greaves et al.
patent: 6119196 (2000-09-01), Muller et al.
patent: 6151319 (2000-11-01), Dommety et al.
patent: 6175902 (2001-01-01), Runaldue et al.
patent: 6185185 (2001-02-01), Bass et al.
patent: 6636503 (2003-10-01), Shiran et al.
patent: 6760341 (2004-07-01), Erimli et al.
patent: 6832256 (2004-12-01), Toga
patent: 7120155 (2006-10-01), Sokol et al.
patent: 2003/0118028 (2003-06-01), Neal et al.
patent: 0312917 (1989-04-01), None
patent: 0465090 (1992-01-01), None
patent: 0752796 (1997-01-01), None
patent: 0849917 (1998-06-01), None
patent: 0853441 (1998-07-01), None
patent: 0854606 (1998-07-01), None
patent: 0859492 (1998-08-01), None
patent: 0862349 (1998-09-01), None
patent: 0907300 (1999-04-01), None
patent: 1 001 571 (1999-08-01), None
patent: 2 725 573 (1996-04-01), None
patent: 4-189023 (1992-07-01), None
patent: WO 97/50214 (1997-12-01), None
patent: WO 98/09473 (1998-03-01), None
patent: WO 99/00938 (1999-01-01), None
patent: WO 99/00939 (1999-01-01), None
patent: WO 99/00944 (1999-01-01), None
patent: WO 99/00945 (1999-01-01), None
patent: WO 99/00948 (1999-01-01), None
patent: WO 99/00949 (1999-01-01), None
patent: WO 99/00950 (1999-01-01), None
patent: WO9900936 (2001-06-01), None
“High-Speed CMOS Circuit for 1.2-Gb/s 16×16 ATM Switching,” Alain Chemarin et al. 8107 IEEE Journal of Solid-State Circuits 27(Jul. 1992), No. 7, New York, US, pp. 1116-1120.
“Local Area Network Switch Frame Lookup Technique for Increased Speed and Flexibility,” 700 IBM Technical Disclosure Bulletin 38(Jul. 1995), No. 7, Armonk, NY, US, pp. 221-222.
“Queue Management for Shared Buffer and Shared Multi-buffer ATM Switches,” Yu-Sheng Lin et al., Department of Electronics Engineering & Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan, R.O.C., Mar. 24, 1996, pp. 688-695.
“A 622-Mb/s 8×8 ATM Switch Chip Set with Shared Multibuffer Architecture,” Harufusa Kondoh et al., 8107 IEEE Journal of Solid-State Circuits 28(Jul. 1993), No. 7, New York, US, pp. 808-814.
“Catalyst 8500 CSR Architecture,” White Paper XP-002151999, Cisco Systems Inc. 1998, pp. 1-19.
“Computer Networks,” A.S. Tanenbaum, PRENTICE-HALL INT., USA, XP-002147300(1998), Sec. 5.2-Sec. 5.3, pp. 309-320.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method and apparatus of inter-chip bus shared by message... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus of inter-chip bus shared by message..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus of inter-chip bus shared by message... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3908781

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.