Semiconductor memory device and process for producing the same

Details Semiconductor memory device and process for producing the same Semiconductor memory device and process for producing the same

1981-01-12

1985-04-23

Munson, Gene M.

357 2311, 357 41, H01L 2978, H01L 2702

Patent

active

045133042

DESCRIPTION:

BRIEF SUMMARY
DESCRIPTION



Background of the Invention

The present invention relates to a semiconductor memory device, particularly one-transistor/one-capacitor-memory cells, and the process for producing the same.
In one-transistor/one-capacitor memory cells, one bit of the memory device is provided by one MOS transistor (1) and one memory capacitor (2), as illustrated in FIG. 1. The circuit of the one-transistor/one-capacitor-memory cell is the simplest structure in dynamic memory devices. As illustrated in FIG. 1, the gate of each MOS transistor (1) is connected to a word line (W) and the source of each MOS transistor (1) is connected to a bit line (B). The word lines (W) and the bit lines (B) perpendicularly cross each other in the plan view of the one-transistor/one-capacitor-memory device. One bit of the one-transistor/one-capacitor-memory cells has, for example, a structure such as illustrated in FIGS. 2A and 2B. In FIGS. 2A and 2B, which respectively illustrate the plan and cross sectional views of the one bit mentioned above, the reference numerals 3, 4 and 5 indicate a capacitor electrode, an insulating film for the capacitor consisting of silicon dioxide, and an electric charge-storing region of a silicon substrate, respectively.
The capacitor electrode (3), the insulating film (4) for the capacitor, and the charge-storing region (5) constitute an MOS capacitor. The capacitance of the MOS capacitor is determined by the capacitor electrode (3), the insulating film (4), and the charge-storing region (5). When the voltage applied to the capacitor electrode (3) is more than the threshold voltage of the electric charge-storing region (5), beneath the insulating film (4), electric charges are stored in this portion. The electric charges are caused to move from the electric-charge storing portion (5) to the source (7) in accordance with the potential applied to the gate electroce (6). The information "0" or "1" can be detected depending upon the movement or non-movement of the electric charges.
Each of the memory cells is surrounded by a thick insulating film (8) at the circumference thereof and is hence isolated from adjacent memory cells. The bit line (B) connects the sources (7) of the MOS transistors with each other. The gate electrode (6) of the MOS transistor is a portion of the word lines (W) shown in FIGS. 2A and 2B. It is known in U.S. Pat. No. 3,996,658 to overlap the gate electrode (6) over the capacitor electrode (3) in a memory cell of a semiconductor memory device.
In a memory cell having the conventional structure as explained above, an oxide film is usually used as the insulating film (4) for the capacitor. However, since the breakdown electric field of the oxide film is approximately from 2 MV/cm to 5 MV/cm, it is difficult to reduce the thickness of the oxide film from the conventional thickness, i.e. from 200 to 500 .ANG.. Consequently, it is difficult to increase the capacitance per unit area of the insulating film higher than a certain value, which is the most serious impediment to reducing the size of the memory cell.
For the production of memory cells, it is necessary to repeat, several times, the steps of mask alignment using photolithographic techniques. It is necessary to reckon beforehand the error which occurs in the alignment of masks. The dimensions of the memory cells must be increased as a result of the error in the mask alignment.
The patterning (i.e., the defining of the borders) of the capacitor electrode (3), which consists of polycrystalline silicon, is particularly important for the dimensions of the memory cells. When the patterning of the insulating film (8) for isolation (which is carried out in the step preceeding the step of forming the capacitor electrode (3)) deviates from the proper theoretical position of the insulating film (8), the dimensions of the capacitor electrode (3), and hence the capacitance of the capacitor, can be smaller than that required. Accordingly, the insulating film (8) must be formed by taking into consideration the error in mask alignment, and t

REFERENCES:
patent: 3996658 (1976-12-01), Takei et al.
patent: 4021789 (1977-05-01), Furman et al.
patent: 4094057 (1978-06-01), Bhattacharyya et al.
patent: 4115795 (1978-09-01), Masuoka et al.
patent: 4151607 (1979-04-01), Koyanagi et al.
patent: 4240092 (1980-12-01), Kuo
Vogl, "Making a One-Device Memory Cell", IBM Technical Disclosure Bulletin, vol. 18, (5/76), pp. 3953-3954.

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