Select lines for NAND memory devices

Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...

Reexamination Certificate

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C438S257000

Reexamination Certificate

active

11191505

ABSTRACT:
A NAND memory array has a select line coupled to each of a plurality of NAND strings of memory cells of the memory array. The select line has a select gate at each intersection of one of the plurality of NAND strings and the select line. The select line further includes first and second conductive layers separated by a dielectric layer, and a contact that extends from a third conductive layer, disposed on the second conductive layer, to the first conductive layer. The contact is formed in a hole that passes through the second conductive layer and the dielectric layer and that terminates at the first conductive layer. The contact electrically connects the first and second conductive layers. The hole can have a slot shape so that the contact spans two or more NAND strings of the plurality of NAND strings.

REFERENCES:
patent: 5776795 (1998-07-01), Chi et al.
patent: 6355522 (2002-03-01), Chang
patent: 6709729 (2004-03-01), Baruch
patent: 7060561 (2006-06-01), Lee
patent: 2004/0014286 (2004-01-01), Park

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