Apparatus for multiple-divisor prescaler

Details Apparatus for multiple-divisor prescaler Apparatus for multiple-divisor prescaler

2007-10-30

2007-10-30

Nguyen, Linh My (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Pulse multiplication or division

C327S115000, C327S117000, C377S048000

Reexamination Certificate

active

11419762

ABSTRACT:
Disclosed is an apparatus for multiple-divisor prescaler, which includes an odd/even core divider, a divisor control logic unit, an odd number inserted mechanism, and an n-order divided-by-2 divider with changeable trigger edges. This invention uses a clock toggle mechanism to vary the trigger edges of each divided-by-2 divider in the n-order divider, and associates the odd/even core divider to realize the multiple-divisor prescaler apparatus. Thereby, it achieves the purpose of being divided by 30/31. In addition, it increases the divisor range up to 2n−1+2 and 2n+1 through the use of the clock toggle mechanism.

REFERENCES:
patent: 5425074 (1995-06-01), Wong
patent: 6768353 (2004-07-01), Carralero et al.
patent: 6970025 (2005-11-01), Magoon et al.
patent: 7113009 (2006-09-01), Sun et al.
patent: 2005/0253630 (2005-11-01), Huang et al.

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