Method of making self-aligned, planarized contacts for semicondu

Details Method of making self-aligned, planarized contacts for semicondu Method of making self-aligned, planarized contacts for semicondu

1989-04-13

1990-12-11

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 41, 437 56, 437193, 437228, 148DIG50, 148DIG141, H01L 21312

Patent

active

049771086

ABSTRACT:
A novel process is provided for fabricating contacts (46s, 40g, 46d) in a novel, completely self-aligned, planarized configuration for transistors (14), with self-aligned interconnections (46c). The process of the invention permits higher packing densities, and allows feature distances to approach 0.5 .mu.m and lower.
A unique combination of masks in conjunction with a multi-layer structure (28) formed on the surface of a semiconductor wafer (16), the multi-layer structure including a buried etch-stop layer therein (28b), defines the source (18), gate (22), and drain (20) elements and their geometry relative to each other and to interconnects. Polysilicon plug (40, 46) contacts through slots in the multi-structure layer permit vertical contact to be made to the various elements. Silicidation (56) of the polysilicon plugs reduces series resistance in the vertical direction and permits strapping of N.sup.+ and P.sup.+ polysilicon plugs.

REFERENCES:
patent: 4231051 (1980-10-01), Custode et al.
patent: 4634496 (1987-01-01), Mase et al.
patent: 4780429 (1988-10-01), Roche et al.
patent: 4803173 (1989-02-01), Sill et al.
patent: 4849369 (1989-07-01), Jeuch et al.

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