Method for manufacturing interconnection structure in semiconduc

Details Method for manufacturing interconnection structure in semiconduc Method for manufacturing interconnection structure in semiconduc

1989-08-09

1990-12-11

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437189, 437194, 437195, 437203, H01L 2160

Patent

active

049771051

ABSTRACT:
Conductive layers (5a, 8a) included in a multi-layer structure (30a) are electrically interconnected through an conductive connection wall (13a) provided in a contact hole (12) and contacting the side surface (22) of the multi-layer structure (30a). The upper conductive layer (11a) existing on the multi-layer structure (30a) and the lower conductive layer (3) existing under the multi-layer structure (30a) are electrically interconnected through a conductive film (11b) provided in the contact hole (12). These two interconnections are insulated from each other by an insulating film (18) provided on the connection wall (13a).

REFERENCES:
patent: 4545114 (1985-10-01), Ito et al.
patent: 4619037 (1986-10-01), Taguchi et al.
patent: 4641170 (1987-02-01), Ogura et al.
patent: 4830972 (1989-05-01), Hamasaki
patent: 4832789 (1989-05-01), Cochran et al.
"A VLSI Bipolar Metallization Design . . . ", IBM J. Res. Develop., vol. 26, No. 3, May 1982, pp. 362-371.
"VLSI Multilevel Metallization", Solid State Technology, Dec. 1984, pp. 93-100.

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