Method for fabricating semiconductor memory device

Details Method for fabricating semiconductor memory device Method for fabricating semiconductor memory device

1989-10-31

1990-12-11

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 40, 437 41, 437 44, 437 47, 437 60, 437228, H01L 21265

Patent

active

049770993

ABSTRACT:
A method for fabricating a semiconductor memory device which includes a single substrate, at least one memory cell including at least one MOS transistor formed on the single substrate, and a peripheral circuit having at least one MOS transistor formed on the single substrate, comprises the steps of forming on the single substrate a gate electrode for each of the MOS transistors of the memory cell and the peripheral circuit, iono-implanting impurities at a low dosage by using the gate electrodes as a mask so as to forming a low impurity concentration of source/drain regions of the MOS transistors of the memory cell and the peripheral circuit, depositing a mask layer to cover an area of the memory cell, and ion-implanting impurities at a high dosage by using the mask layer as a mask, so as to dope impurities to only the source/drain regions of the MOS transistor of the peripheral circuit, so that the MOS transistor of the memory cell has the source/drain regions of a low impurity concentration, and the MOS transistor of the peripheral circuit has the source/drain regions including a high impurity concentration portion.

REFERENCES:
patent: 4435896 (1984-03-01), Paullo et al.
patent: 4466177 (1984-08-01), Chao
patent: 4536947 (1985-08-01), Bohr et al.
patent: 4758898 (1988-06-01), Parillo et al.

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