Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2007-08-28
2007-08-28
Abrams, Neil (Department: 2839)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
Reexamination Certificate
active
10852370
ABSTRACT:
A wiring substrate can include a substrate material, which can have a first surface and a second surface. A plurality of first electrically conductive elements can be disposed on the first surface, and a plurality of second electrically conductive elements can be disposed on the second surface. Ones of the first conductive elements can be electrically connected through the substrate material to ones of the second conductive elements. A mechanism can be located in a first region, which can be a center region, of the second surface of the substrate material. The mechanism can be configured to engage a control member. First activation of the control member can apply an adjustable pulling force to the first region, and second activation of the control member can apply an adjustable pushing force to the first region. The mechanism can be or can include a threaded stud, and the control member can be or can include a threaded nut configured to engage the threaded stud.
REFERENCES:
patent: 3998377 (1976-12-01), Metz
patent: 4518914 (1985-05-01), Okubo et al.
patent: 4751457 (1988-06-01), Veenendaal
patent: 4922192 (1990-05-01), Gross et al.
patent: 4947481 (1990-08-01), Ikedo et al.
patent: 5094536 (1992-03-01), MacDonald
patent: 5148103 (1992-09-01), Pasiecznik, Jr.
patent: 5321453 (1994-06-01), Mori et al.
patent: 5461326 (1995-10-01), Woith et al.
patent: 5521522 (1996-05-01), Abe et al.
patent: 5642054 (1997-06-01), Pasiecznik, Jr.
patent: 5804983 (1998-09-01), Nakajima et al.
patent: 5828226 (1998-10-01), Higgins et al.
patent: 5974662 (1999-11-01), Eldridge et al.
patent: 6040700 (2000-03-01), Berar
patent: 6043668 (2000-03-01), Carney
patent: 6087840 (2000-07-01), Mizuta
patent: 6122823 (2000-09-01), Kira et al.
patent: 6144212 (2000-11-01), Mizuta
patent: 6160412 (2000-12-01), Martel et al.
patent: 6166552 (2000-12-01), O'Connell
patent: 6189876 (2001-02-01), Frazier
patent: 6509751 (2003-01-01), Mathieu et al.
patent: 6774651 (2004-08-01), Hembree
patent: 802419 (1997-10-01), None
patent: 59149070 (1984-10-01), None
patent: 1152271 (1989-10-01), None
patent: 2226996 (1990-09-01), None
patent: 3065659 (1991-03-01), None
patent: 3292406 (1991-12-01), None
patent: 4207047 (1992-07-01), None
patent: 4294559 (1992-10-01), None
patent: 529406 (1993-02-01), None
patent: 05-264590 (1993-10-01), None
patent: 650990 (1994-02-01), None
patent: 10-031034 (1998-02-01), None
patent: WO96/15458 (1996-05-01), None
U.S. Appl. No. 09/527,931, filed Mar. 17, 2000, Mathieu et al.
Eldridge Benjamin N.
Grube Gary W.
Mathieu Gaetan L.
Abrams Neil
Burraston N. Kenneth
FormFactor Inc.
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