Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1994-12-28

1996-06-04

Popek, Joseph A.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

36523003, 36523006, G11C 800

Patent

active

055239803

ABSTRACT:
A NAND-cell type EEPROM having a plurality of bit lines, a plurality of control gate lines intersecting with the bit lines, and a plurality of memory cells driven by applying a potential to the control gate lines for selectively storing data, supplying data to the bit lines and receiving data therefrom. The memory cells form a plurality of cell units. The memory cells constituting each cell unit are connected in series to one bit line by a common selecting gate transistor. A plurality of data latch circuits are provided on the bit lines, respectively, for storing data to be written into the memory cells selected by the control gate lines. Further, a plurality of selecting gate drivers are provided to correspond to the cell units, respectively, for driving the control gate lines. A row decoder decodes row addresses for driving the selecting gate drivers and the control gate lines. A plurality of block-address latch circuits are provided to correspond to the selecting gate drivers, respectively, for temporarily storing signals derived from a row address by the row decoder, thereby to select at least two of the selecting gate drivers at the same time in order to write data.

REFERENCES:
patent: 4958326 (1990-09-01), Sakurai
patent: 5034928 (1991-07-01), Isobe
patent: 5043942 (1991-08-01), Iwata et al.
patent: 5073873 (1991-12-01), Nogami

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