Generating multi-phase clock signals using hierarchical delays

Details Generating multi-phase clock signals using hierarchical delays Generating multi-phase clock signals using hierarchical delays

2007-02-06

2007-02-06

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S159000, C327S161000, C327S272000, C327S278000

Reexamination Certificate

active

11313291

ABSTRACT:
Circuits and methods for generating multi-phase clock signals using digitally-controlled hierarchical delay units (HDs) are provided. A plurality of serially-coupled HDs outputs clock signals that are phase-shifted relative to a reference clock signal. Each HD includes either one or two variable delay lines that provide coarse phase adjustment of an associated input signal. Each HD also includes one or more phase mixers that provide fine phase adjustment of the input signal.

REFERENCES:
patent: 4985639 (1991-01-01), Renfrow et al.
patent: 5355097 (1994-10-01), Scott et al.
patent: 5463337 (1995-10-01), Leonowich
patent: 5663665 (1997-09-01), Wang et al.
patent: 5751665 (1998-05-01), Tanoi
patent: 5789927 (1998-08-01), Belcher
patent: 5872488 (1999-02-01), Lai
patent: 6100736 (2000-08-01), Wu et al.
patent: 6194916 (2001-02-01), Nishimura et al.
patent: 6194947 (2001-02-01), Lee et al.
patent: 6295328 (2001-09-01), Kim et al.
patent: 6313688 (2001-11-01), Lee et al.
patent: 6326826 (2001-12-01), Lee et al.
patent: 6366148 (2002-04-01), Kim
patent: 6393083 (2002-05-01), Beukema
patent: 6512408 (2003-01-01), Lee et al.
patent: 6573771 (2003-06-01), Lee et al.
patent: 6618283 (2003-09-01), Lin
patent: 6621315 (2003-09-01), Heo et al.
patent: 6642760 (2003-11-01), Alon et al.
patent: 6661863 (2003-12-01), Toosky
patent: 6762633 (2004-07-01), Lee
patent: 6768361 (2004-07-01), Kwak
patent: 6791381 (2004-09-01), Stubbs et al.
patent: 6812753 (2004-11-01), Lin
patent: 6952127 (2005-10-01), Lee
patent: 6956418 (2005-10-01), Kwak
patent: 6982578 (2006-01-01), Lee
patent: 6982579 (2006-01-01), Lee
patent: 2003/0219088 (2003-11-01), Kwak
Jong-Tae Kwak et al., “A Low Cost High Performance Register-Controlled Digital DLL for 1 Gbps x32 DDR SDRM”, The 8thKorean Conference on Semiconductors, Feb. 2001.
Ramin Farjad-Rad et al. “A Low-Power Multiplying DLL for Low-Jitter Multigigahertz Clock Generation in Highly Integrated Digital Chips”, IEEE Journal of Solid-State Circuits, vol. 37, No. 12, pp. 1804-1812, Dec. 2002.

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