Non-volatile memory utilizing a thin film, floating gate, amorph

Static information storage and retrieval – Floating gate

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365113, 365222, 257 52, 257316, G11C 1134

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active

055239706

ABSTRACT:
A memory controller generates control and address signal for accessing a non-volatile memory having a plurality of addressable cells. Each cell of the non-volatile memory includes a floating gate transistor (e.g., Q15) capable of storing charge (representing a binary 1 or 0) for extended, although not indefinite, periods of time. To refresh any charge that leaks off the floating gate, refresh circuitry (e.g., Q17-Q19) is provided to restore the charge on the gate to its original logical state. This refresh circuitry may be activated at "power-up." Each of the transistors in the memory are preferably thin film, amorphous silicon, "N" type transistors, including the floating gate transistor.

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Arun Madan and Melvin P. Shaw, "The physics and applicatins of amorphous semiconductors", Academic Press 1988, Chapters 2 and 3 (pp. 35-317).

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