Power saving zero pruning algorithm for fast fourier...

Details Power saving zero pruning algorithm for fast fourier... Power saving zero pruning algorithm for fast fourier...

2007-11-20

2007-11-20

Ngo, Chuong D. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

10682622

ABSTRACT:
A fast Fourier transform (FFT) circuit from which unneeded butterfly computation modules can be effectively pruned for specific applications. Each module that is not needed is pruned by injecting zero signals into it, thereby minimizing the power dissipated in the pruned circuit. A multiplexer integrated into each butterfly module output (or input) line allows the line signal to be either forced to zero or allowed to carry a nonzero signal.

REFERENCES:
patent: 5808925 (1998-09-01), Ito et al.
patent: 6747946 (2004-06-01), Kaneko et al.
patent: 2003/0145026 (2003-07-01), Jin

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