DLL-based programmable clock generator using a...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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C327S264000, C327S283000, C327S161000

Reexamination Certificate

active

11194628

ABSTRACT:
A DLL-based programmable clock generator using a threshold-trigger delay element and an edge combiner is proposed. A threshold-trigger delay element with full swing complementary output signals consumes no dc power. It exhibits small delay error resulting reduced out jitter. It also increases the linearity of delay time versus control voltage. The circular edge combiner can multiply the input signal at a lower supply voltage. The rise and fall time of output signal are more symmetrical. It also present the multiplication factor of the clock generator can be easy to choose with the increasing of the number of delay elements.

REFERENCES:
patent: 6617903 (2003-09-01), Kawamura
patent: 6633189 (2003-10-01), Gradinariu et al.
patent: 6728334 (2004-04-01), Zhao
patent: 2003/0184337 (2003-10-01), Huang
John G. Maneatis, “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques”, IEEE Journal of Solid-State Circuits, vol. 31, No. 11, Nov. 1996.
Mohammad Maymandi-Nejad et al., “A Digitally Programmable Delay Element: Design and Analysis”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, No. 5, Oct. 2003.
Mark G. Johnson et al., “A Variable Delay Line PLL for CPU-Coprocessor Synchronization”, IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988.
Jørgen Christiansen, “An Integrated High Resolution CMOS Timing Generator Based on an Array of Delay Locked Loops”, IEEE Journal of Solid-State Circuits, vol. 31, No. 7, Jul. 1996.
Deog-Kyoon Jeong et al., “Design of PLL-Based Clock Generation Circuits”, IEEE Journal of Solid-State Circuits, vol. SC-22, No. 2, Apr. 1987.
George Chien et al., “A 900-MHZ Local Oscillator Using a DLL-Based Frequency Multiplier Technique for PCS Applications”, IEEE Journal of Solid-State Circuits, vol. 35, No. 12, Dec. 2000.
David J. Foley et al., “CMOS DLL-Based 2-V 3.2-ps Jitter 1-GHZ Clock Synthesizer and Temperature-Compensated Tunable Oscillator”, IEEE Journal of Solid-State Circuits, vol. 36, No. 3, Mar. 2001.
Chulwoo Kim et al., “Low-Power Small-Area ± 7.28ps Jitter 1GHz DLL-Based Clock Generator”, ISSCC 2002/ Session 8/ High Speed Timing /8.3.
Hong-Yi Huang, “Threshold Triggers and Accelerator for Deep Submicron Interconnection”, 2002 IEEE.
Cheng-Jia et al., “Capacitor Coupling Threshold Logic”, 2002 IEEE.
Pietro Andreani et al., “On the Use of MOS Varactors in RF VCO's”, IEEE Journal of Solid-State Circuits, vol. 35, No. 6, Jun. 2000.
Yongsam Moon et al., “An All-Analog Multiphase Delay-Locked Loop Using a Replica Delay Line for Wide-Range Operation and Low-Jitter Performance”, IEEE Journal of Solid-State Circuits, vol. 35, No. 3, Mar. 2000.
Guang-Kaai Dehng et al., “Clock-Deskew Buffer Using a SAR-Controlled Delay-Locked Loop”, IEEE Journal of Solid-State Circuits, vol. 35, No. 8, Aug. 2000.
Floyd M. Gardner, “Charge-Pump Phase-Lock Loops”, IEEE Transactions on Communications, vol. COM-28, No. 11, Nov. 1980.
Hee-Tae Ahn et al., “A Low-Jitter 1.9-V CMOS PLL for UltraSPARC Microprocessor Applications”, IEEE Journal of Solid-State Circuits, vol. 35, No. 3, Mar. 2000.
Woogeun Rhee, “Design of High-Performance CMOS Charge Pumps in Phase-Locked Loops”, 1999 IEEE.
Manuel Mota et al., “A High-Resolution Time Interpolator Based on a Delay Locked Loop and an RC Delay Line”, IEEE Journal of Solid-State Circuits, vol. 34, No. 10, Oct. 1999.
Hong-Yi Huang et al., “A DLL-Based Programmable Clock Generator Using Threshold-Trigger Delay Element and Circular Edge Combiner”, 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits(AP-ASIC2004)/ Aug. 4-5, 2004.

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