Nonvolatile semiconductor memory device and a method of word...

Details Nonvolatile semiconductor memory device and a method of word... Nonvolatile semiconductor memory device and a method of word...

2007-12-25

2007-12-25

Phung, Anh (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180

Reexamination Certificate

active

11295567

ABSTRACT:
A nonvolatile semiconductor memory device having a first circuit for selecting one from the plurality of blocks, the first circuit having a plurality of transistors connected to word lines connected to some of the nonvolatile memory cells and a second circuit for generating a first voltage V1, a second voltage V2and a third voltage V3(V3<V2<V1). The first voltage is applied to a source or drain of one of the transistors connected to a selected word line at a timing of programming. The second voltage is applied to sources or drains of some of the transistors connected to non-selected word lines at the timing of programming. The third voltage is applied to a source or a drain of one of the transistors connected to at least one of the non-selected word lines at the timing of programming.

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U.S. Appl. No. 11/295,567, filed Dec. 7, 2005, Hosono.

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