System and method for improved branch performance in...

Details System and method for improved branch performance in... System and method for improved branch performance in...

2007-12-11

2007-12-11

Chan, Eddie (Department: 2183)

Electrical computers and digital processing systems: processing

Instruction issuing

C712S233000

Reexamination Certificate

active

10443673

ABSTRACT:
A system and method for improved branch performance in pipelined computer architectures is presented. Priority bits are set during code execution that corresponds to an upcoming branch instruction. A priority bit may be associated with a register, a resource, or a microsequencer. An instruction selector compares one or more priority bits with each of a plurality of instructions in order to identify particular instructions to execute that make registers and resources available for an upcoming branch instruction. The instruction selector then prioritizes the identified instructions and the pipeline executes in instructions in the prioritized order.

REFERENCES:
patent: 5485629 (1996-01-01), Dulong
patent: 5625837 (1997-04-01), Popescu et al.
patent: 5745726 (1998-04-01), Shebanow et al.
patent: 6487715 (2002-11-01), Chamdani et al.
Structured Computer Organization by Andrew S. Tanenbaum.

Affiliated with

Also associated with

Rating

System and method for improved branch performance in... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System and method for improved branch performance in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for improved branch performance in... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3883067