Electrical computers and digital processing systems: processing – Processing architecture – Long instruction word
Reexamination Certificate
2007-02-20
2007-02-20
Chan, Eddie (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Long instruction word
C712S208000
Reexamination Certificate
active
09721152
ABSTRACT:
To decode a composite VLIW packet, assembly code is provided for the bit patterns corresponding to each individual instruction in the packet. The bit pattern for the template in the packet is then matched against a known template. The known template uniquely corresponds to a known syntax corresponding to one of a plurality of known syntaxes, where the plurality of known syntaxes are arranged as a plurality of first level nodes in a tree structure, where each of a plurality of second level nodes in said tree structure includes a combination of instruction types, and where each of a plurality of third level nodes in said tree structure includes an instruction type. The known syntax is then matched to a resolved packet syntax using the tree structure. The resolved packet syntax is then used to provide assembly code associated with the execution of the combination of instructions in the packet.
REFERENCES:
patent: 5922065 (1999-07-01), Hull et al.
patent: 6457173 (2002-09-01), Gupta et al.
Petrov, “Code Compaction and Parallelization for VLIW/DSP Chip Architectures,” Jun. 1999, pp. 38-40.
Aditya et al., “Automatic Design of VLIW and EPIC Instruction Formats,” Apr. 2000, pp. 71-82.
Chan Eddie
Farjami & Farjami LLP
Huisman David J.
Mindspeed Technologies Inc.
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