Transistor having vertical junction edge and method of...

Details Transistor having vertical junction edge and method of... Transistor having vertical junction edge and method of...

2007-06-12

2007-06-12

Jackson, Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

C257S333000, C257S374000, C257S510000, C257S520000, C257S499000

Reexamination Certificate

active

10751141

ABSTRACT:
Techniques for forming devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an oxide. Cavities may be formed in the oxide and filled with a conductive material, such a heavily doped polysilicon. Vertical junctions are formed between the polysilicon and the exposed substrate at the trench edges such that during a thermal cycle, the heavily doped polysilicon will out-diffuse doping elements into the adjacent single crystal silicon advantageously forming a diode extension having desirable properties.

REFERENCES:
patent: 5841150 (1998-11-01), Gonzalez et al.
patent: 6096596 (2000-08-01), Gonzalez
patent: 6118135 (2000-09-01), Gonzalez et al.
patent: 6271566 (2001-08-01), Tsuchiaki
patent: 6429104 (2002-08-01), Auberton-Herve
patent: 6468879 (2002-10-01), Lamure et al.
patent: 2002/0190344 (2002-12-01), Michejda et al.

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