Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2007-12-25
2007-12-25
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Interconnection arrangements
C365S230030
Reexamination Certificate
active
11627727
ABSTRACT:
A semiconductor device includes a memory cell array, first word lines, second word lines and interconnection switching region. The memory cell array includes electrically rewritable nonvolatile memory cells. Each first word line is connected in common to memory cells of a corresponding row. Second word lines correspond to the respective first word lines. The second word lines are formed of a second interconnection of a layer different from that of the first interconnection. An interconnection switching region is provided between the first word lines and the second word lines. The interconnection switching region connect selected portions of the first interconnection and the second interconnection. The interconnection switching region has a multilayered interconnection structure in which the first word lines cross the second word lines to change at least part of layout positions.
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Kabushiki Kaisha Toshiba
Le Vu A.
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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