Pipelined analog-to-digital converter with mid-sampling...

Details Pipelined analog-to-digital converter with mid-sampling... Pipelined analog-to-digital converter with mid-sampling...

2007-10-16

2007-10-16

Mai, Lam T. (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S160000

Reexamination Certificate

active

11161502

ABSTRACT:
A double-sampled pipeline analog-to-digital conversion (ADC) system and method in which latching of the intrastage digital quantization signals occurs approximately midway the leading and trailing edges of the clock signals.

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patent: 6881942 (2005-04-01), Huang et al.
Cormac S.G. Conroy, “A High Spped Parallel Pipeline A/D Converter Technique in CMOS,” Memorandum No. UCB/ERL M94/9, Feb. 15, 1994, pp. 53-68, Electronics Research Laboratory, University of California, Berkeley.
Stephen H. Lewis and Paul r. Gray, “A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter,” JSS, vol. SC-22, No. 6, Dec. 1987 pp. 954-961.
Roubik Gregorian, “Introduction to CMOS OP-AMPS and Comparators,” Ch. 5, 1999, pp. 175-213, John Wiley & Sons, Inc., New York, Chichester, Weinheim, Brisbane, Singapore, Toronto.
William C. Black, Jr., et al., “Time Interleaved Converter Arrays,” IEEE JSSCC, vol. SC-15, No. 6, Dec. 1980, pp. 1022-1029.

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