Interconnection substrate and fabrication method thereof

Details Interconnection substrate and fabrication method thereof Interconnection substrate and fabrication method thereof

2007-06-19

2007-06-19

Picardat, Kevin M. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S750000, C438S652000, C438S642000

Reexamination Certificate

active

10947177

ABSTRACT:
An interconnection substrate includes: an interconnection layer region where at least a first conductor layer and a second conductor layer are vertically stacked in that order on a substrate, with the first conductor layer and second conductor layer containing conductive particles and a binder, wherein the first conductor layer and second conductor layer stacked in the interconnection layer region have conductive particles different in average particle size from each other. As a result, only an intended region can have low resistance.

REFERENCES:
patent: 6214636 (2001-04-01), Sawayama et al.
patent: 6891465 (2005-05-01), Hatayama
patent: 61-224491 (1986-10-01), None

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