PLL clock generator circuit and clock generation method

Details PLL clock generator circuit and clock generation method PLL clock generator circuit and clock generation method

2007-08-07

2007-08-07

Shingleton, Michael B. (Department: 2815)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

C331S002000, C331S008000, C331S010000, C331S018000, C331S025000

Reexamination Certificate

active

10649672

ABSTRACT:
A clock generator circuit is provided wherein a comparison clock signal is generated by comparing a standard clock signal and an operating clock signal. The comparison clock signal is converted into a current signal. The current signal is converted to multiple current signals and an operating clock signal having multiple varying frequencies is generated based on the multiple current signals.

REFERENCES:
patent: 5978425 (1999-11-01), Takla
patent: 6160861 (2000-12-01), McCollough
patent: 6229400 (2001-05-01), McCollough et al.
patent: 6404294 (2002-06-01), Sha et al.
patent: 2002/0079973 (2002-06-01), Higashi et al.
patent: 2000-101424 (2000-04-01), None

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