Plating buss and a method of use thereof

Details Plating buss and a method of use thereof Plating buss and a method of use thereof

2007-02-27

2007-02-27

Arbes, Carl J. (Department: 3729)

Metal working

Method of mechanical manufacture

Electrical device making

C029S825000, C029S830000, C029S852000

Reexamination Certificate

active

10861847

ABSTRACT:
The present invention relates generally to a plating buss design and method for minimizing short circuit problems in PCB panel singulation. More particularly, the invention encompasses a serpentine plating buss which increases the PCB singulation process window thereby minimizing short circuit problems due to indexing errors caused by occasional manufacturing and equipment alignment problems. The serpentine plating buss design therefore increases board yield.

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patent: 1 381 260 (2004-01-01), None
Stacked Orthogonal Serpentine Delay Lines with Vias for Two-dimensional Microchannel Plate Readout, a paper by M. Lampton et al in Rev Scientific Instruments vol. 71, No. 12, Dec. 2000, pp. 4611-4619.

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