Reduced dead-cycle, adaptive phase tracking method and...

Details Reduced dead-cycle, adaptive phase tracking method and... Reduced dead-cycle, adaptive phase tracking method and...

2007-06-26

2007-06-26

Ha, Dac V. (Department: 2611)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

C375S325000, C375S371000, C375S375000

Reexamination Certificate

active

10763905

ABSTRACT:
A data sampling method and circuit employing an oversampling clock to oversample a data signal, a phase tracker for use with or in a data sampling circuit, and a method for identifying a sequence of best sampling positions for sampling a data signal from signal samples generated using an oversampling clock. In some embodiments, data indicative of the phase of at least one of the oversampling clock's sampling positions relative to the center of the data eye are low-pass filtered in a manner determined by the data signal's bit rate. In other embodiments, the number of dead cycles of the phase tracker decision loop is reduced by generating possible solutions in parallel and moving the feedback point so as to occur as late as practical, or the phase tracker ignores a sample set when updating its determination of the best sampling position when the sample set indicates that the data signal has less than a predetermined number of transitions during a corresponding tracking period.

REFERENCES:
patent: 5905769 (1999-05-01), Lee et al.
patent: 6907089 (2005-06-01), Jensen et al.
patent: 7180966 (2007-02-01), Vallet et al.
patent: 2006/0039513 (2006-02-01), Sheen et al.
patent: 2006/0062327 (2006-03-01), Dally

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