Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
Reexamination Certificate
2007-11-06
2007-11-06
Kindred, Alford (Department: 2181)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Commitment control or register bypass
C712S214000, C712S216000, C712S219000
Reexamination Certificate
active
10807093
ABSTRACT:
One embodiment of the present invention provides a system that dynamically adjusts the aggressiveness of an execute-ahead processor. If a data-dependent stall condition is encountered during program execution, the system enters an execute-ahead mode, wherein instructions that cannot be executed because of the unresolved data dependency are deferred, and other non-deferred instructions are executed in program order. If a non-data-dependent stall condition is encountered during execute-ahead mode, the system enters a scout mode, wherein instructions are speculatively executed to prefetch future loads, but results are not committed to the architectural state of the execute-ahead processor. On the other hand, if an unresolved data dependency is resolved during the execute-ahead mode, enters a deferred mode and executes deferred instructions. During this deferred mode, if some instructions are deferred again, the system determines whether to resume execution in the execute-ahead mode. If it determines to do so, the system resumes execution in the execute-ahead mode, and otherwise resumes execution in a non-aggressive mode.
REFERENCES:
patent: 2005/0081195 (2005-04-01), Chaudhry et al.
patent: 0 357 188 (1990-03-01), None
IBM Technical Disclosure Bulletin entitled “Deferred decodeing”, vol. 27, No. 10B, Mar. 1985 IBM Corp., pp. 6257-6258, XP-000885126.
Publication entitled “Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors”, by Onur Mutlu et al., Proceedings of The Ninth International Symposium on High-Performance computer Architeture, IEEE, 2002.
Publication entitled “Beating in-order Stalls with “Flea-Flicker” two-pass Pipelining”, by Ronald D. Barnes et al., Proceedings of the 36thInternational Symposium on Microarchitecture, IEEE, 2003.
Caprioli Paul
Yip Sherman H.
Kindred Alford
Moll Jesse
Park Vaughan & Fleming LLP
Sun Microsystems Inc.
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