PLL circuit and program for same

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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C327S156000

Reexamination Certificate

active

11340633

ABSTRACT:
A reference voltage signal (VpmpR), which is obtained by applying the output signal UPB/UP of a phase/frequency detection circuit (PFD) as a constantly locked state signal to a replica charge pump circuit (CPR) and then integrating, is compared in a correction voltage generation circuit (CMP) with a PLL circuit control voltage signal (Vpmp) for controlling a voltage-controlled oscillation circuit (VCO) by a desired voltage, this PLL circuit-controlled voltage signal being obtained by applying the output signal UPB/DN of the phase/frequency detection circuit as input to a charge pump circuit (CP) and then integrating, and the correction voltage signal (Vcmp) that is the result of the comparison then controls a charge pump bias circuit (CPBias) that controls the bias currents of the charge pump circuit and replica charge pump circuit.

REFERENCES:
patent: 5438299 (1995-08-01), Shimada et al.
patent: 6107862 (2000-08-01), Mukainakano et al.
patent: 6111468 (2000-08-01), Tanishima
patent: 6771114 (2004-08-01), Watarai
patent: 6829318 (2004-12-01), Kawahara
patent: 06-291649 (1994-10-01), None
patent: 10-248240 (1998-09-01), None
patent: 11-103251 (1999-04-01), None
patent: 11-225069 (1999-08-01), None
patent: 2003-087115 (2003-03-01), None

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