Delay locked loop using a FIFO circuit to synchronize...

Details Delay locked loop using a FIFO circuit to synchronize... Delay locked loop using a FIFO circuit to synchronize...

2007-11-06

2007-11-06

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S161000

Reexamination Certificate

active

11211825

ABSTRACT:
Embodiments of the present invention generally provide improved techniques and circuit configurations for a delay-locked loop (DLL) circuit. In one embodiment, a first phase difference between an input clock signal and an output clock signal is measured. Based on the first phase difference, a first phase adjustment setting is stored in a first FIFO and a second phase adjustment setting is stored in a second FIFO. The first phase adjustment setting is applied to adjust a phase of the input clock signal and the adjusted clock signal passes through one or more delay elements. The second phase adjustment setting is applied to further adjust the delayed input clock signal. As a result, the first phase adjustment setting and the second phase adjustment setting are applied correctly with respect to an edge of the clock signal passing through the DLL circuit.

REFERENCES:
patent: 5604775 (1997-02-01), Saitoh et al.
patent: 6727738 (2004-04-01), Tsukikawa
patent: 6836166 (2004-12-01), Lin et al.

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