Method and system for a pad structure for use with a...

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For plural devices

Reexamination Certificate

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Details

C257S786000, C257S773000, C257S924000, C257SE25015, C361S782000

Reexamination Certificate

active

10973735

ABSTRACT:
Systems and methods for substrate layers used in attaching devices to a semiconductor package are disclosed. A novel pad structure may be employed on a substrate layer which has pads, each pad having a common electrical potential. Multiple pad openings may be employed on a single pad, allowing the attachment of multiple terminals of one or more decoupling capacitors to a single pad. These pads and pad openings can be arranged according to the type of decoupling capacitor employed, allowing a greater total pad area to be utilized in conjunction with a set of pad openings, while simultaneously allowing the multiple pad openings on the pad to be placed closer together, reducing the ESL and ESR of the path between the semiconductor and the decoupling capacitors, increasing the mechanical reliability of the semiconductor package and allowing a higher density of decoupling capacitors to be coupled to a given area.

REFERENCES:
patent: 5010447 (1991-04-01), Wallace
patent: 6300677 (2001-10-01), Salem
patent: 6664628 (2003-12-01), Khandros et al.
patent: 6900991 (2005-05-01), Patel et al.
patent: 1994-44169 (1994-06-01), None
patent: 2002-359450 (2002-12-01), None
AVK Corporation, Low Inductance Capacitors Catalogue 0612/0508 IDC, pp. 6 & 7.

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