SRAM based cache for DRAM routing table lookups

Details SRAM based cache for DRAM routing table lookups SRAM based cache for DRAM routing table lookups

Filed on

2007-10-23

Date issued

2007-10-23

Examiner

Duong, Frank (Department: 2616)

Patent Class

Multiplex communications

SubClass

Pathfinding or routing

SubSubClass

Switching a message which includes an address header

Other Related Categories

C370S395310, C370S395320

Type

Reexamination Certificate

Status

active

Patent number

10052793

Description

ABSTRACT:
A router (101) includes one or more input ports (104) and one or more output ports (112). The router (101) includes a lookup table (105) to determine routing of the incoming packets or cells. The lookup table is implemented in dynamic random access memory (DRAM) with a portion implemented as static random access memory (SRAM) (202, 204). The SRAM (204) is used to store a first search level of destination addresses. Once the first search level in SRAM (204) has been exhausted, the search moves to the DRAM portion (202).

REFERENCES:
patent: 5528592 (1996-06-01), Schibler et al.
patent: 5588130 (1996-12-01), Fujishima et al.
patent: 5875117 (1999-02-01), Jones et al.
patent: 5914956 (1999-06-01), Williams
patent: 6078532 (2000-06-01), Rivers et al.
patent: 6154746 (2000-11-01), Berchtold et al.
patent: 6404752 (2002-06-01), Allen et al.
patent: 6691206 (2004-02-01), Rubinstein
patent: 6985483 (2006-01-01), Mehrotra et al.
Gupta et al, Routing Lookups in Hardware at Memory Access Speeds, IEEE, pp. 1240-1247, 1998.
Chiueh et al, High-Performance IP Routing Table Lookup Using CPU Caching, IEEE, pp. 1421-1428, 1999.

Affiliated with

Also associated with

Rating

SRAM based cache for DRAM routing table lookups does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with SRAM based cache for DRAM routing table lookups, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and SRAM based cache for DRAM routing table lookups will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3862537