Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2007-08-07

2007-08-07

Phung, Anh (Department: 2824)

Static information storage and retrieval

Addressing

Sequential

C365S233100, C365S191000

Reexamination Certificate

active

11340471

ABSTRACT:
An internal address generating circuit sequentially generates internal addresses in the burst read operation, with an external address being set as an initial value. A memory core has plural memory cells and sequentially outputs, in response to activation of a column selection signal, data read from the memory cells corresponding to the internal addresses in the burst read operation. In the burst read operation, a column control circuit in a memory core control circuit repeats activation of the column selection signal for a certain period during an activation period of an external control signal and forcibly deactivates the column selection signal in synchronization with deactivation of the external control signal. In the burst read operation, an operation state control circuit in the memory core control circuit deactivates an operation state control signal after a predetermined time has elapsed from the deactivation of the external control signal.

REFERENCES:
patent: 2001/0047464 (2001-11-01), Shinozaki
patent: 2004/0165472 (2004-08-01), Yamazaki
patent: 2005/0226090 (2005-10-01), Lee
patent: 2006/0203576 (2006-09-01), Nishimura et al.
patent: 1 406 267 (2004-04-01), None
patent: 2000-207882 (2000-07-01), None
patent: 2004-259400 (2004-09-01), None

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