Method for programming multi-bit charge-trapping memory cell...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185180, C365S185030, C365S185130

Reexamination Certificate

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11172421

ABSTRACT:
A programming voltage is applied to source and drain in order to generate hot-hole injection at one end of the channel of a memory cell. The undesired programming of a neighboring memory cell is avoided by the application of an intermediate inhibit voltage to an adjacent bitline. This is done by precharging all the bitlines to the inhibit voltage, either by successively applying the inhibit voltage to every bitline individually or by applying both the upper and the lower programming voltage to one half of the bitlines and then short-circuiting all the bitlines to produce an intermediate voltage.

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Yeh, C.C., et al., “PHINES: A Novel Low Power Program/Erase, Small Pitch, 2-Bit per Cell Flash Memory,” 2002 IEEE, 4 pages.
Willer, J., et al., “110nm NROM Technology for Code and Data Flash Products,” 2004 IEEE, Symposium on VLSI Technology Digest of Technical Papers, pp. 76-77.

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