Circuit layout structure

Details Circuit layout structure Circuit layout structure

2007-12-11

2007-12-11

Kebede, Brook (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

C257S206000, C257SE27013

Reexamination Certificate

active

10537124

ABSTRACT:
Main-transistors M1and M2are divided into sub-transistors that are arrayed in a matrix with four rows and four columns to form four cells so that each of the cells is formed of four of the sub-transistors that have a common center. This can realize a layout configuration that is as good in matching of the main-transistors M1and M2as a four-segment layout scheme and takes small pattern area.

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patent: 08-274259 (1996-10-01), None
patent: 2001-168197 (2001-06-01), None
Mao-Feng et al. (2001) “Current Mirror Layout Strategies for Enhancing Matching Performance,” Analog Integrated Circuits and Signal Processing 28, pp. 9-26.
Marcel J. M. Pelgrom et al. (1989) “Matching Properties of MOS Transistors,” IEEE Journal of Solid-State Circuits 24(5), pp. 1433-1439.

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