Phase-locked loop having a bandwidth related to its input...

Details Phase-locked loop having a bandwidth related to its input... Phase-locked loop having a bandwidth related to its input...

2007-12-25

2007-12-25

Pascal, Robert (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

C331S017000, C331S034000, C331S17700V, C327S156000

Reexamination Certificate

active

11154314

ABSTRACT:
An integrated circuit includes a phase-locked loop (PLL) in which the loop bandwidth of the PLL is proportional to the input frequency of the PLL. The PLL includes a phase/frequency detector (PFD), a charge pump, a loop filter, and a voltage-controlled oscillator (VCO) that generates the PLL output clock. The VCO includes a current scaling block that scales the sum of a variable current, which is proportional to the loop filter voltage, and a fixed current. The frequency of the PLL output clock is a function of the current output from the current scaling block. Since the same scaling factor is applied to both the fixed current and the variable current, the gain from the loop filter voltage to the PLL output frequency is proportional to the PLL output frequency, and thus the loop bandwidth of the PLL is proportional to the PLL input frequency.

REFERENCES:
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patent: 5504459 (1996-04-01), Gersbach et al.
patent: 5696468 (1997-12-01), Nise
patent: 5942949 (1999-08-01), Wilson et al.
patent: 6933798 (2005-08-01), Hammes et al.
patent: 2005/0185749 (2005-08-01), Convent et al.
Maneatis, John G.; “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques”; IEEE Journal of Solid-State Circuits; Nov. 1996; pp. 1723-1732; vol. 31, No. 11; USA.

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