Triple inverter pierce oscillator circuit suitable for CMOS

Details Triple inverter pierce oscillator circuit suitable for CMOS Triple inverter pierce oscillator circuit suitable for CMOS

2007-02-27

2007-02-27

Chang, Joseph (Department: 2817)

Oscillators

Electromechanical resonator

Crystal

C331S1160FE

Reexamination Certificate

active

10937163

ABSTRACT:
An oscillator circuit is disclosed which can be formed using discrete field-effect transistors (FETs), or as a complementary metal-oxide-semiconductor (CMOS) integrated circuit. The oscillator circuit utilizes a Pierce oscillator design with three inverter stages connected in series. A feedback resistor provided in a feedback loop about a second inverter stage provides an almost ideal inverting transconductance thereby allowing high-Q operation at the resonator-controlled frequency while suppressing a parasitic oscillation frequency that is inherent in a Pierce configuration using a “standard” triple inverter for the sustaining amplifier. The oscillator circuit, which operates in a range of 10–50 MHz, has applications for use as a clock in a microprocessor and can also be used for sensor applications.

REFERENCES:
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patent: 2004/0090279 (2004-05-01), Seki
Kurt Wessendorf and Tom Payne, “Oscillator design techniques allow high-frequency applications,” Mar. 1998 RF Design magazine.

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