Programmable strength output buffer for RDIMM address register

Static information storage and retrieval – Interconnection arrangements

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C365S189050

Reexamination Certificate

active

11195910

ABSTRACT:
A programmable strength output buffer intended for use within the address register of a memory module such as a registered DIMM (RDIMM). The output signals of an array of such buffers drive respective output lines that are connected to the address or control pins of several RAM chips. The programmable buffers vary the strength of at least some of the output signals in response to a configuration control signal, such that the output signals can be optimized for the loads to which they will be connected.

REFERENCES:
patent: 4707620 (1987-11-01), Sullivan et al.
patent: 5519338 (1996-05-01), Campbell et al.
patent: 5632019 (1997-05-01), Masiewicz
patent: 5958026 (1999-09-01), Goetting et al.
patent: 6684263 (2004-01-01), Horowitz et al.
patent: 2004/0243753 (2004-12-01), Horowitz et al.
patent: 2005/0060601 (2005-03-01), Gomm
patent: 2005/0259504 (2005-11-01), Murtugh et al.
patent: 2006/0280004 (2006-12-01), Washburn et al.
patent: 2007/0111606 (2007-05-01), Goodwin
patent: 1273063 (1990-08-01), None
JEDEC Standard, Definition of the SSTU32864 1.8-V Configurable Registered Buffer for DDR2 RDIMM Applications, JEDEC Solid State Technology Association, JESD82-7A, Oct. 2004, pp. 1-16.
JEDEC Standard, Definition of the SSTU32866 1.8-V Configurable Registered Buffer with Parity Test for DDR2 RDIMM Applications, JEDEC Solid State Technology Association, JESD82-10, Nov. 2004, pp. 1-32.
JEDEC Standard No. 21C, PC2-3200/PC2-4300 Registered DIMM Design Specification, Apr. 2004, pp. 1-67.
Dabral, S. and Maloney, T. J.,Basic ESD and I/O Design, New York, John Wiley & Sons, Inc., pp. 162-165, 1998.
“DDR SDRAM Specification, Version 1.31,” Samsung Electronics, Nov. 3, 2001, pp. 1-55.
“DDR2 Registered Memory Modules, Data Sheet, Rev. 0.85,” Infineon, Apr. 200, pp. 1-33.
“Spartan-II 2.5V FPGA Family: Functional Description, DS001-2 (v2.2)”. Xilinx, Sep. 3, 2003, pp. 1-45.
“Interfacing the QDR with Altora APEX20KE,” Cypress Semiconductor Corp., Mar. 12, 2001, 7 pps.
“Interfacing the QDR with Xilinx Spartan-II FPGA,” Cypress Semiconductor Corp., Feb. 21, 2000, 4 pps.
“EIA/JEDEC Standard,” EIA/JESD8-7, Electronics Industries Association, Feb. 1977, 7 pps.
“CY7C1316V18, 18-Mb DDR-II SRAM Two-word Burst Architecture,” Cypress Semiconductor Corp., Jul. 31, 2002, pp. 1-24.
“Quad-Data-Rate SRAM Subsystems Maximize System Performance,” Electronic Design, Feb. 7, 2000, 6 pps.
“TI is the First Supplier with Logic Register Components for Evaluation in DDR-II DIMM Designs,” Embedded Star, Sep. 26, 2002, pp. 1-2.
“Digitally Adjustable Resistors in CMOS for High-Performance Applications,” IEEE Journal of Solid-State Circuits, vol. 27, No. 8, Aug. 1992, pp. 1176-1185.
“PC133 SDRAM Registered DIMM, Design Specification, Revision 1.4,” JEDEC Standard No. 21-C, Feb. 2002, 74 pps.
“Output Buffer Impedance Control and Noise Reduction Using a Speed-Locked Loop,” International Solid-State Circuits Conference, 2004, 9 pps.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Programmable strength output buffer for RDIMM address register does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programmable strength output buffer for RDIMM address register, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable strength output buffer for RDIMM address register will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3850369

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.