Method and apparatus for examining semiconductor apparatus...

Data processing: measuring – calibrating – or testing – Testing system – Of circuit

Reexamination Certificate

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C702S117000

Reexamination Certificate

active

10411272

ABSTRACT:
The invention performs an AC stress test assuming the CMOS operation and an AC stress test using a ring oscillator (R.O.) between a DC stress test method using single semiconductor elements and an aging test method. The deterioration of a semiconductor apparatus can be estimated highly precisely by separately performing the AC stress test assuming the CMOS operation on OFF-stress and ON-stress.

REFERENCES:
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patent: 2001/0032329 (2001-10-01), Lee et al.
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patent: 2001-284457 (2001-10-01), None
M. Inuishi et al., “A High Performance and Highly Reliable Dual Gate CMOS with Gate/N' Overlapped LDD Applicable to the Cryogenic Operation,” International Electron Devices Meeting, Dec. 3-6, 1989, IEDM Technical Digest, pp. 773-776.
T. Hori, “1/4-μm LATID (LArge Tilt-angle Implanted Drain) Technology For 3.3-V Operation,” International Electron Devices, Meeting, Dec. 3-6, 1989, IEDM Technical Digest, pp. 777-780.

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