Integrated circuit with means for reducing ESD damage

Details Integrated circuit with means for reducing ESD damage Integrated circuit with means for reducing ESD damage

1991-09-27

1992-08-25

Wilczewski, Mary

Fishing, trapping, and vermin destroying

437239, 357 2313, 357 54, H01L 2170, H01L 2190, H01L 2198

Patent

active

051418983

ABSTRACT:
An integrated-circuit (IC) chip having means to prevent or mitigate damage from electrostatic discharge (ESD) employing a thick dielectric coating of insulative oxide between the surface of the chip substrate and the metallization film used to make contact with regions of the substrate. At least a portion of this layer is formed at temperatures below 700.degree. C. The coating is sufficiently thick everywhere that its breakdown voltage is greater than the breakdown voltage of any junction in the substrate. This assures that the breakdown caused by ESD will always occur in the junction, which is self healing, rather than in the dielectric coating, where the damage could be permanent.

REFERENCES:
patent: 4435447 (1984-03-01), Ito et al.
patent: 4455568 (1984-06-01), Shiota
patent: 4602267 (1986-07-01), Shirato
patent: 4720737 (1988-01-01), Shirato
patent: 4729009 (1988-03-01), Ang
patent: 4806999 (1989-02-01), Strauss
Wolf et al. Silicon Processing for the VLSI Era, vol. 1 Process Technology, Lattice Press, 1986, p. 183.

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