Nonvolatile semiconductor memory device performing erase...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185220, C365S185290

Reexamination Certificate

active

11358206

ABSTRACT:
A nonvolatile semiconductor memory device includes a control circuit configured to perform a first block erase operation that erases nonvolatile memory cells together in a lump such that threshold voltages of the memory cells are set lower than a first erase verify voltage, to check whether a threshold voltage of each of the nonvolatile memory cells is lower than a first erase-degree-check voltage after the first block erase operation, to perform a first write-back operation in response to a check result indicating that the threshold voltage is lower than the first erase-degree-check voltage, thereby raising the threshold voltage above a voltage higher than the first erase-degree-check voltage, and to perform a second block erase operation that erases the nonvolatile memory cells together in a lump after the first write-back operation such that the threshold voltages of the memory cells are set lower than a second erase verify voltage.

REFERENCES:
patent: 6172911 (2001-01-01), Tanaka et al.
patent: 6356480 (2002-03-01), Sakakibara et al.
patent: 6466484 (2002-10-01), Sakakibara et al.
patent: 7139201 (2006-11-01), Tanaka et al.
patent: 2001-184876 (2001-07-01), None
patent: 2003-162896 (2003-06-01), None

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