Step-down voltage output circuit

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage

Reexamination Certificate

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Details

C327S534000, C327S536000, C327S537000, C327S538000, C327S539000, C323S313000, C363S059000

Reexamination Certificate

active

10923848

ABSTRACT:
To provide a step-down voltage output circuit which causes no latch-up phenomenon for the period between activation of a power supply and complete start of operation of a charge pump circuit. The step-down voltage output circuit of the present invention has the charge pump circuit with a first oscillator; a timer circuit in which a timer period is set according to an oscillating frequency of the above-mentioned first oscillator; and an N-channel MOS transistor in which one N-type diffusion layer is connected to an output terminal of the above-mentioned charge pump circuit, the other N-type diffusion layer is connected to ground potential, and a gate electrode is connected to an output terminal of the above-mentioned timer circuit to become conductive for the above-mentioned timer period.

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patent: 5650741 (1997-07-01), Nakamura et al.
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patent: 5920226 (1999-07-01), Mimura
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patent: 2002/0130700 (2002-09-01), Walimbe et al.
patent: 2004/0165407 (2004-08-01), Umeda et al.
patent: 2006/0044031 (2006-03-01), Cheung et al.
patent: 5-29360 (1993-02-01), None
patent: 7-78472 (1995-03-01), None

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