Power semiconductor packaging method and structure

Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – With housing or external electrode

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S180000, C257S181000, C257S727000, C257S728000, C361S709000, C361S760000

Reexamination Certificate

active

11205903

ABSTRACT:
A semiconductor chip packaging structure comprising a dielectric film having one or more through holes aligned with the one or more contact pads of at least one power semiconductor chip. A patterned electrically conductive layer adjacent to the dielectric film has one or more electrically conductive posts which extend through the one or more though holes aligned with the contact pads to electrically couple the conductive layer to the contact pads. In certain embodiments, one or more air gaps may be formed between the dielectric film and the active surface of the at least one power semiconductor chip. Methods for fabricating the semiconductor chip packaging structure are also disclosed.

REFERENCES:
patent: 4835704 (1989-05-01), Eichelberger et al.
patent: 5169678 (1992-12-01), Cole et al.
patent: 5258647 (1993-11-01), Wojnarowski et al.
patent: 5324687 (1994-06-01), Wojnarowski
patent: 5449427 (1995-09-01), Wojnarowski et al.
patent: 5497033 (1996-03-01), Fillion et al.
patent: 5532512 (1996-07-01), Fillion et al.
patent: 5554305 (1996-09-01), Wojnarowski et al.
patent: 5576517 (1996-11-01), Wojnarowski et al.
patent: 5637922 (1997-06-01), Fillion et al.
patent: 5672546 (1997-09-01), Wojnarowski
patent: 5785787 (1998-07-01), Wojnarowski et al.
patent: 5949133 (1999-09-01), Wojnarowski
patent: 6002162 (1999-12-01), Takahashi et al.
patent: 6229203 (2001-05-01), Wojnarowski
patent: 6297459 (2001-10-01), Wojnarowski et al.
patent: 6306680 (2001-10-01), Fillion et al.
patent: 6410356 (2002-06-01), Wojnarowski et al.
patent: 2002/0121691 (2002-09-01), Wojnarowski et al.
A. Werling et al., “Fast implementation of the single scatter simulation algorithm and its use in interative image reconstruction of PET data,” Institute of Physics Publishing, Phys. Med. Biol. 47 (2002), pp. 2247-2960.
M. Popall et al., “Ormocer®s—Inorganic-Organic Hybrid materials for e/o-Interconnection-Technology,” Mil. Cryst. and Liq. Cryst, 2000. vol. 354, pp. 123-142.
Fraunhofer Institut Silicatforschung Annual Report 2003, Ormocers, pp. 44-48.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Power semiconductor packaging method and structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Power semiconductor packaging method and structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Power semiconductor packaging method and structure will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3847366

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.