Method of fabricating a FET having a high trap concentration int

Details Method of fabricating a FET having a high trap concentration int Method of fabricating a FET having a high trap concentration int

1990-08-06

1992-08-25

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 40, 437133, 437912, H01L 21265, H01L 2120

Patent

active

051418797

ABSTRACT:
A FET having a high trap concentration interface layer and method of fabrication includes a semi-insulating gallium arsenide substrate having a high trap concentration interface layer formed therein. An non-intentionally doped buffer layer, also comprised of gallium arsenide, is then formed on the interface layer and is followed by the formation of a doped aluminum gallium arsenide layer thereon. A source, a gate and a drain are then formed on the FET layers. The FET and method disclosed herein are especially applicable for low current (5-1000 microamp) operation of microwave low-noise FETs.

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Horio et al., "Numerical Simulation of GaAs MESFET's on the Semi-Insulating Substrate Compensated by Deep Traps", IEEE Transactions on Electron Devices, vol. 35, No. 11, Nov. 1988, pp. 1778-1785.
Leigh et al. "Interfacial Effects Related to Backgating in Ion-Implemented GaAs MESFET's ", IEEE Transactions on Electron Devices, vol. Ed. 32 No. 9, Sep. 1985, pp. 1835-1840.
Morgan et al. "Ion Implantation and Damage in GaAs" in Gallium Arsenide Material, Services, and Circuits, edited by Howes et al., John Wiley and Sons, p. 173.
Evian 1982 "Semi-Insulating II-V Materials" edited by Ebeid et al., Shiva Publishing Limited, 1982, p. 341.

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