Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2007-11-27
2007-11-27
Zarabian, Amir (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185190, C365S185280, C365S185060
Reexamination Certificate
active
11124220
ABSTRACT:
A dynamic programming method for a non-volatile storage device is described. Memory cells are provided arrayed in R rows. Sub bit lines are provided coupled to voltage supply lines through select circuits. During program operation, the select circuits are switched such that one or more of the source side sub bit line or the drain side sub bit line is floating when all other program voltages are applied to a selected cell.
REFERENCES:
patent: 5587947 (1996-12-01), Chang et al.
patent: 6108239 (2000-08-01), Sekariapuram et al.
patent: 6114724 (2000-09-01), Ratnakumar
patent: 6255166 (2001-07-01), Ogura et al.
patent: 6459622 (2002-10-01), Ogura et al.
patent: 6549463 (2003-04-01), Ogura et al.
patent: 6873550 (2005-03-01), Mihnea
patent: 6898126 (2005-05-01), Yang et al.
Ogura, et al. “Twin MONOS: a nitride based dual bit flash memory”, Nov. 15-17, 2004, Non-Volatile Memory Technology Symposium, 2004, 157-160.
Ogura, et al. “Twin MONOS cell with dual control gates”, Jun. 13-15, 2000, Symposium on VLSI Technology, 2000, 122-123.
Tatsuya Ishii, et al., “A 126.6 mm2AND-type 512 M6 Flash Memory with 1.8V Power Supply”ISSCC2001.
Ogura Nori
Ogura Seiki
Ackerman Stephen B.
Halo LSI, Inc.
Saile Ackerman LLC
Weinberg Michael
Zarabian Amir
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