STM mapping circuit and method

Details STM mapping circuit and method STM mapping circuit and method

2007-02-06

2007-02-06

Jung, Min (Department: 2663)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S466000, C370S505000

Reexamination Certificate

active

10106037

ABSTRACT:
An STM mapping circuit is disclosed having a configuration that includes: a packet length detection circuit for generating byte effectiveness information that indicates whether byte data are effective data or not; routing circuits for generating routing information for rearranging byte data in a prescribed order while using byte effectiveness information to eliminate pad bytes; packet filter circuits for taking in packet data for each logical channel in accordance with channel number signals that indicate which logical channel the packet data belong to; M×M switches for sorting packet data for logical channel in a prescribed order while removing pad bytes in accordance with routing information; and packet memories that hold, for each logical channel, packet data that have been sorted by the M×M switches.

REFERENCES:
patent: 6097739 (2000-08-01), Yamashita
patent: 6414966 (2002-07-01), Kulkarni et al.
patent: 6584118 (2003-06-01), Russell et al.
patent: 2002/0016852 (2002-02-01), Nishihara
patent: 2002/0159473 (2002-10-01), Roberts et al.

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