Pulse or digital communications – Synchronizers
Reexamination Certificate
2007-12-25
2007-12-25
Ghayour, Mohammed (Department: 2611)
Pulse or digital communications
Synchronizers
C713S400000, C375S219000, C375S355000
Reexamination Certificate
active
10376835
ABSTRACT:
A system and method for establishing a known timing relationship between two clock signals, wherein a first clock signal is operable to clock data transfer operations from a transmitter domain to a receiver domain and a second clock signal is operable to be transported to the receiver domain. Circuitry is provided for detecting an edge in a global framework clock (GFC) signal that is supplied to the transmitter domain. A common alignment signal is manufactured that is based at least in part upon the GFC signal. A multiplexer and register arrangement is operable to output the second clock signal in response to the common alignment signal which is also used for gating the data transfer operations clocked by the first clock signal.
REFERENCES:
patent: 4558445 (1985-12-01), Novick
patent: 4694472 (1987-09-01), Torok et al.
patent: 5432823 (1995-07-01), Gasbarro et al.
patent: 5459764 (1995-10-01), Ohgami et al.
patent: 5822381 (1998-10-01), Parry et al.
patent: 5887040 (1999-03-01), Jung et al.
patent: 6078623 (2000-06-01), Isobe et al.
patent: 6081141 (2000-06-01), Young
patent: 6104253 (2000-08-01), Hall et al.
patent: 6130552 (2000-10-01), Jefferson et al.
patent: 6178206 (2001-01-01), Kelly et al.
patent: 6255880 (2001-07-01), Nguyen
patent: 6285172 (2001-09-01), Torbey
patent: 6334163 (2001-12-01), Dreps et al.
patent: 6396887 (2002-05-01), Ware et al.
patent: 6463092 (2002-10-01), Kim et al.
patent: 6584575 (2003-06-01), Meyer et al.
patent: 6661262 (2003-12-01), Curran
patent: 6668292 (2003-12-01), Meyer et al.
patent: 6715096 (2004-03-01), Kuge
patent: 6775300 (2004-08-01), Kuo
patent: 6775339 (2004-08-01), Wildes et al.
patent: 6895062 (2005-05-01), Wilson
patent: 6937680 (2005-08-01), Fong et al.
patent: 7139308 (2006-11-01), Doblar et al.
patent: 2001/0033584 (2001-10-01), Dally
patent: 2002/0141515 (2002-10-01), Enam et al.
patent: 2003/0043926 (2003-03-01), Terashima et al.
Search Report; Australian Patent Office; Nov. 2, 2005; 4 pages.
Examination Report; Australian Patent Office; Nov. 2, 2005; 4 pages.
Saint-Laurent et al.; “On the Micor-Architectural Impact of Clock Distribution Using Multiple PLLs”; Proceedings of the International Conference on Computer Design; 2001; 7 pages.
Elboim et al.; “A Clock Tuning Circuit for System-on-Chip”; VLSI Systems Research Center; 2002; pp. 607-610.
Ghayour Mohammed
Hewlett--Packard Development Company, L.P.
Vlahos Sophia
LandOfFree
System and method for establishing a known timing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for establishing a known timing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for establishing a known timing... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3842310