Method for setting erasing pulses and screening erasing...

Details Method for setting erasing pulses and screening erasing... Method for setting erasing pulses and screening erasing...

2007-06-26

2007-06-26

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185330, C365S185300

Reexamination Certificate

active

11251453

ABSTRACT:
Method for determining the number of applications of erasing pulses, including extracting two pairs of the accumulated number of the erasing pulses Np and the ratio Re of the number of erased memory cells in the target block to be erased after the accumulated number of the erasing pulses Np has been applied, converting the two ratios Re into normalized variables S(Re) through normalizing the random variables of the normal distribution probability with standard deviations, converting the two accumulated numbers of the erasing pulses Np into common logarithms Log(Np), calculating a common logarithm Log(Nt) through extrapolating from two sets of coordinates [Log(Np), S(Re)], and determining the number of applications of the remaining erasing pulses so that the extrapolation erasing pulse number Nt is the target accumulated number of applications of erasing pulses.

REFERENCES:
patent: 5053990 (1991-10-01), Kreifels et al.
patent: 5448712 (1995-09-01), Kynett et al.
patent: 6646926 (2003-11-01), Keays
patent: 2-10596 (1990-01-01), None
Mukherjee, S. et al. (1985). “A Single Transistor EEPROM Cell and its Implementation in a 512K CMOS EEPROM,”IEDM Technical Digest85:616-619.

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