Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2007-08-21

2007-08-21

Elms, Richard T. (Department: 2824)

Static information storage and retrieval

Floating gate

C365S185290, C365S189060

Reexamination Certificate

active

11245195

ABSTRACT:
A semiconductor memory device includes a memory cell array with electrically rewritable and non-volatile memory cells arranged therein, and a bit line control circuit connected to a bit line of the memory cell array to control and detect the bit line voltage in accordance with operation modes, wherein the bit line control circuit comprises a first transistor and a second transistor with a breakdown voltage higher than that of the first transistor, the second transistor being disposed between the first transistor and a bit line in the memory cell array to be serially connected to the first transistor, and wherein a connection node between the first and second transistors is fixed in potential at a data erase time.

REFERENCES:
patent: 6907497 (2005-06-01), Hosono et al.
patent: 2002/0172077 (2002-11-01), Ha
patent: 2004/0170056 (2004-09-01), Shibata et al.
patent: 2003-249083 (2003-09-01), None
Tomoharu Tanaka, et al., “A Quick Intelligent Page-Programming Architecture and a Shielded Bitline Sensing Method for 3 V-Only NAND Flash Memory”, IEEE Journal of Solid-State Circuits, vol. 29, No. 11, Nov. 1994, pp. 1366-1373.

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