Method for manufacturing MOS transistors with high breakdown vol

Details Method for manufacturing MOS transistors with high breakdown vol Method for manufacturing MOS transistors with high breakdown vol

1995-05-22

1996-06-04

Thomas, Tom

Fishing, trapping, and vermin destroying

437 41, 437 56, 437 59, H01L 21265

Patent

active

055232485

ABSTRACT:
A semiconductor device in which low voltage elements and high voltage elements are formed on the same substrate. To simplify the manufacturing process of semiconductor devices and to improve the punch through voltage resistance between elements, when high voltage elements and low voltage elements are formed on the same semiconductor substrate, during the process for injecting p-type impurity into semiconductor substrate in the low voltage sections, at first a mask pattern having openings above the low voltage sections and openings above the element separating areas of the high voltage sections is formed, then p-type impurity is injected into the semiconductor substrate from above the mask pattern, followed by heat-treatment of the semiconductor substrate to diffuse p-type impurity into the semiconductor substrate. Thereby, channel stop diffusion layers comprising p-type impurity layer are formed under the element separating areas formed in the high voltage sections.

REFERENCES:
patent: 5004701 (1991-04-01), Motokawa
patent: 5073510 (1991-12-01), Kwon et al.
patent: 5173438 (1992-12-01), Sandhu
patent: 5223451 (1993-06-01), Uemura et al.
patent: 5254495 (1993-10-01), Lur et al.
patent: 5268585 (1993-12-01), Yamauchi
patent: 5358890 (1994-10-01), Sivan et al.
patent: 5372951 (1994-12-01), Anjum et al.

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