Method of fabricating self-aligned planarized well structures

Details Method of fabricating self-aligned planarized well structures Method of fabricating self-aligned planarized well structures

1995-08-24

1996-06-04

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437 57, 437924, 437 70, H01L 218238

Patent

active

055232477

ABSTRACT:
A method of forming a planarized self-aligned integrated circuit structure suitable for forming CMOS circuitry is provided. The method involves using first and second barrier layers to define the dopant regions for first and second wells, respectively. The first barrier can be formed of a silicon nitride layer covered with a silicon oxide layer. The first barrier layer prevents doping of the silicon wafer except in those regions not covered by the first barrier layer (i.e., the first wells). The second barrier layer is formed by oxidizing the silicon wafer. Only the regions not covered by the first layer are oxidized. The second wells are defined by the second barrier layer. Because some of the silicon of the first wells is consumed to form the second barrier layer, the height of the first wells following the formation of the second barrier layer is less than that of the second wells. To equalize the height of the first and second wells, and thereby planarize the wafer, the height of the second wells is reduced to substantially the same height as the first wells. The second wells can be reduced to the same height as the first wells using wet silicon etching, dry silicon etching or oxidation followed by an oxide removal step.

REFERENCES:
patent: 4516316 (1985-05-01), Haskell
patent: 4558508 (1985-12-01), Kinney et al.
patent: 4929565 (1990-05-01), Parrillo
patent: 5413944 (1995-05-01), Lee

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