Process for fabricating high-performance facet-free small-sized

Details Process for fabricating high-performance facet-free small-sized Process for fabricating high-performance facet-free small-sized

1995-04-26

1996-06-04

Nguyen, Tuan H.

Fishing, trapping, and vermin destroying

437 89, 437 90, 148DIG11, H01L 21265

Patent

active

055232450

ABSTRACT:
After a formation of a side wall of silicon nitride on an inner periphery defining an emitter hole passing through a silicon nitride layer and a heavily doped polysilicon base electrode layer, a silicon oxide layer on a collector region is isotropically etched so as to expose an upper surface of the collector region and a bottom surface of an inner peripheral portion of the heavily doped polysilicon base electrode layer, and a ring-shaped hollow space beneath the polysilicon base electrode layer is filled with a piece of polysilicon so that the dopant impurity is diffused from the doped polysilicon layer independently from a selective growth of a base layer over the collector region.

REFERENCES:
patent: 5204276 (1993-04-01), Nakajima et al.
patent: 5244533 (1993-09-01), Kimura et al.
patent: 5296391 (1994-03-01), Sato et al.
patent: 5326718 (1994-07-01), Klose et al.
patent: 5424228 (1995-06-01), Imai
patent: 5432104 (1995-07-01), Sato
"A Self-Aligned Selective MBE Technology for High-Performance Bipolar Transistors" by Sato et al; Technical Digest; pp. 607-610.

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