Transistor fabrication method using dielectric protection layers

Details Transistor fabrication method using dielectric protection layers Transistor fabrication method using dielectric protection layers

1994-12-19

1996-06-04

Nguyen, Tuan H.

Fishing, trapping, and vermin destroying

437162, 437909, 148DIG10, 148DIG124, H01L 21265, H01L 4900

Patent

active

055232442

ABSTRACT:
A method for fabricating a super self-aligned bipolar junction transistor which reduces or eliminates emitter defects caused during critical etching steps by providing a non-critically thick dielectric etch stop (protection) layer (116) during all potentially damaging etching steps. An oxide or other dielectric layer (116, 130), is provided above the emitter region (152) of the semiconductor surface (110) during potentially damaging etching steps, such as dry etch procedures used to form critical device structures such as emitter opening 124 and sidewall spacers 146. Non-damaging etching procedures, such as wet etching, are used to remove dielectric protection layers (116, 130) to form less critical device structures, and/or form intermediate layer openings without damaging the silicon surface in the emitter (152), or other critical regions. The dielectric etch stop (protection) layers (116, 130) are non-critically thick and are fully removed from above an extrinsic base region (142) of the device by wet etching before forming the emitter (152) and base regions (142, 144). The method results in a more uniform, lower resistance base connection, higher chip yields, more uniform device properties, and greater device reliability.

REFERENCES:
patent: 4483726 (1984-11-01), Isaac et al.
patent: 4731341 (1988-03-01), Kawakatsu
patent: 4830972 (1989-05-01), Hamasaki
patent: 4975381 (1990-12-01), Taka et al.
patent: 5204276 (1993-04-01), Nakajima et al.
patent: 5244533 (1993-09-01), Kimura et al.
patent: 5296391 (1994-03-01), Sato et al.
patent: 5391503 (1995-02-01), Miwa et al.
Konaka et al., "A 30-ps Si Bipolar IC Using Super Self-Aligned Process Technology," IEEE Trans. Electronic Devices, vol. ED-33, pp. 526-531, Apr. 1986.

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